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FMP3217BA2 Scheda tecnica(PDF) 11 Page - FIDELIX |
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FMP3217BA2 Scheda tecnica(HTML) 11 Page - FIDELIX |
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11 / 12 page ![]() FMP3217BAx CMOS LPRAM Revision 0.3 Feb. 2007 11 16Mb 1Mbx16 100000h-1FFFFFh 1/2 10 1 8Mb 512Kbx16 180000h-1FFFFFh 1/4 11 1 32Mb 2Mbx16 000000h-1FFFFFh Full 00 X 16Mb 1Mbx16 000000h-0FFFFFh 1/2 10 0 8Mb 512Kbx16 000000h-07FFFFh 1/4 11 0 Density Size Address Refresh Section A1,A0 A2 Partial Array Refresh Mode (A3=0, A4=1) Reduced Memory Size Mode (A3=1, A4=1) 3. Deep Power Down Mode Entry/Exit 4. Address Information tZZmin tR A4 /CS /UB, /LB /WE tWC tWR(4 ) tBW tWP(1) tCW(2 ) tAS(3) tAW /ZZ tZZWE Register Write(DPD) Deep Power down start Deep Power down exit Next Cycle 16Mb 1Mbx16 100000h-1FFFFFh 1/2 10 1 8Mb 512Kbx16 180000h-1FFFFFh 1/4 11 1 16Mb 1Mbx16 000000h-0FFFFFh 1/2 10 0 8Mb 512Kbx16 000000h-07FFFFh 1/4 11 0 Density Size Address Refresh Section A1,A0 A2 us - 10 Low Power Mode Time tZZmin us - 200 Operation Recovery Time tR(Deep Power Down Mode only) us 1 0 ZZ low to Write Enable Low tZZWE Units Max Min Description Parameter |
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