XIO2000AI datasheet(102/159 Pages) TAOS

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Spiegazioni elettronici	PCI Express to PCI Bus Translation Bridge

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Classic PCI Configuration Space

April 2007 Revised October 2008

SCPS155C

4.72 Serial IRQ Mode Control Register

This register controls the behavior of the serial IRQ controller. See Table 4−46 for a complete description of

the register contents.

PCI register offset:

E0h

Read-only, Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

Table 4−46. Serial IRQ Mode Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:4

RSVD

Reserved. Returns 0h when read.

3:2†

START_WIDTH

Start frame pulse width. Sets the width of the start frame for a SERIRQ stream.

00 = 4 clocks (default)

01 = 6 clocks

10 = 8 clocks

11 = Reserved

1†

POLLMODE

Poll mode. This bit selects between continuous and quiet mode.

0 = Continuous mode (default)

1 = Quiet mode

0†

DRIVEMODE

Drive mode. This bit selects the behavior of the serial IRQ controller during the recovery cycle.

0 = Drive high (default)

1 = 3-state

† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

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