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XIO2000AI Scheda tecnica(PDF) 103 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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XIO2000AI Scheda tecnica(HTML) 103 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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103 / 159 page  Classic PCI Configuration Space 93 April 2007 Revised October 2008 SCPS155C 4.73 Serial IRQ Edge Control Register This register controls the edge mode or level mode for each IRQ in the serial IRQ stream. See Table 4−47 for a complete description of the register contents. PCI register offset: E2h Register type: Read/Write Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4−47. Serial IRQ Edge Control Register Description BIT FIELD NAME ACCESS DESCRIPTION 15† IRQ15_MODE RW IRQ 15 edge mode 0 = Edge mode (default) 1 = Level mode 14† IRQ14_MODE RW IRQ 14 edge mode 0 = Edge mode (default) 1 = Level mode 13† IRQ13_MODE RW IRQ 13 edge mode 0 = Edge mode (default) 1 = Level mode 12† IRQ12_MODE RW IRQ 12 edge mode 0 = Edge mode (default) 1 = Level mode 11† IRQ11_MODE RW IRQ 11 edge mode 0 = Edge mode (default) 1 = Level mode 10† IRQ10_MODE RW IRQ 10 edge mode 0 = Edge mode (default) 1 = Level mode 9† IRQ9_MODE RW IRQ 9 edge mode 0 = Edge mode (default) 1 = Level mode 8† IRQ8_MODE RW IRQ 8 edge mode 0 = Edge mode (default) 1 = Level mode 7† IRQ7_MODE RW IRQ 7 edge mode 0 = Edge mode (default) 1 = Level mode 6† IRQ6_MODE RW IRQ 6 edge mode 0 = Edge mode (default) 1 = Level mode 5† IRQ5_MODE RW IRQ 5 edge mode 0 = Edge mode (default) 1 = Level mode 4† IRQ4_MODE RW IRQ 4 edge mode 0 = Edge mode (default) 1 = Level mode 3† IRQ3_MODE RW IRQ 3 edge mode 0 = Edge mode (default) 1 = Level mode 2† IRQ2_MODE RW IRQ 2 edge mode 0 = Edge mode (default) 1 = Level mode † These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. |
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