LT3724MPFE datasheet(7/24 Pages) LINER

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LT3724

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PIN FUNCTIONS

VCC (Pin 12): The VCC pin is the internal bias supply decou-

pling node. Use low ESR 1μF ceramic capacitor to decouple

this node to PGND. Most internal IC functions are powered

from this bias supply. An external diode connected from

VCC to the BOOST pin charges the bootstrapped capacitor

during the off-time of the main power switch. Back driving

the VCC pin from an external DC voltage source, such as

the VOUT output of the buck regulator supply, increases

overall efﬁciency and reduces power dissipation in the

IC. In shutdown mode this pin sinks 20μA until the pin

voltage is discharged to 0V.

NC (Pin 13): No Connection.

SW (Pin 14): In step-down applications the SW pin is

connected to the cathode of an external clamping Schottky

diode, the drain of the power MOSFET and the inductor.

The SW node voltage swing is from VIN during the on-

time of the power MOSFET, to a Schottky voltage drop

below ground during the off-time of the power MOSFET.

In start-up and in operating modes where there is insuf-

ﬁcient inductor current to freewheel the Schottky diode, an

internal switch is turned on to pull the SW pin to ground

so that the BOOST pin capacitor can be charged. Give

careful consideration in choosing the Schottky diode to

limit the negative voltage swing on the SW pin.

TG (Pin 15): The TG pin is the bootstrapped gate drive

for the top N-Channel MOSFET. Since very fast high cur-

rents are driven from this pin, connect it to the gate of

the power MOSFET with a short and wide, typically 0.02”

width, PCB trace to minimize inductance.

BOOST (Pin 16): The BOOST pin is the supply for the

bootstrapped gate drive and is externally connected to a

low ESR ceramic boost capacitor referenced to SW pin.

The recommended value of the BOOST capacitor,CBOOST,

is 50 times greater that the total input capacitance of the

topside MOSFET. In most applications 0.1μF is adequate.

The maximum voltage that this pin sees is VIN + VCC,

ground referred.

Exposed Pad (SGND) (Pin 17): The exposed leadframe is

internally connected to the SGND pin. Solder the exposed

pad to the PCB ground for electrical contact and optimal

thermal performance.

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