LT3724MPFE datasheet(6/24 Pages) LINER

6 / 24 page

LT3724

3724fc

PIN FUNCTIONS

VIN (Pin 1): The VIN pin is the main supply pin and should

be decoupled to SGND with a low ESR capacitor located

close to the pin.

NC (Pin 2): No Connection.

SHDN (Pin 3): The SHDN pin has a precision IC enable

threshold of 1.35V (rising) with 120mV of hysteresis. It is

used to implement an undervoltage lockout (UVLO) circuit.

See Application Information section for implementing a

UVLO function. When the SHDN pin is pulled below a

transistor VBE (0.7V), a low current shutdown mode is

entered, all internal circuitry is disabled and the VIN sup-

ply current is reduced to approximately 10μA. Typical

pin input bias current is <10μA and the pin is internally

clamped to 6V.

CSS (Pin 4): The soft-start pin is used to program the sup-

ply soft-start function. The pin is connected to VOUT via a

ceramic capacitor (CSS) and 200kΩ series resistor. During

start-up, the supply output voltage slew rate is controlled

to produce a 2μA average current through the soft-start

coupling capacitor. Use the following formula to calculate

CSS for a given output voltage slew rate:

CSS = 2μA(tSS/VOUT)

See the application section for more information on setting

the rise time of the output voltage during start-up. Shorting

this pin to SGND disables the soft-start function.

BURST_EN (Pin 5): The BURST_EN pin is used to enable

or disable Burst Mode operation. Connect the BURST_EN

pin to ground to enable the burst mode function. Connect

the pin to VCC to disable the burst mode function.

VFB (Pin 6): The output voltage feedback pin, VFB, is

externally connected to the supply output voltage via a

resistive divider. The VFB pin is internally connected to

the inverting input of the error ampliﬁer. In regulation,

VFB is 1.231V.

VC (Pin 7): The VC pin is the output of the error ampliﬁer

whose voltage corresponds to the maximum (peak) switch

current per oscillator cycle. The error ampliﬁer is typically

conﬁgured as an integrator circuit by connecting an RC

network from the VC pin to SGND. This circuit creates the

dominant pole for the converter regulation control loop.

Speciﬁc integrator characteristics can be conﬁgured to

optimize transient response. Connecting a 100pF or greater

high frequency bypass capacitor from this pin to ground

is recommended. When Burst Mode operation is enabled

(see Pin 5 description), an internal low impedance clamp

on the VC pin is set at 100mV below the burst threshold,

which limits the negative excursion of the pin voltage.

Therefore, this pin cannot be pulled low with a low imped-

ance source. If the VC pin must be externally manipulated,

do so through a 1kΩ series resistance.

SGND (Pin 8, 17): The SGND pin is the low noise ground

reference. It should be connected to the –VOUT side of the

output capacitors. Careful layout of the PCB is necessary

to keep high currents away from this SGND connection.

See the Application Information section for helpful hints

on PCB layout of grounds.

SENSE– (Pin 9):

The SENSE– pin is the negative input for

the current sense ampliﬁer and is connected to the VOUT

side of the sense resistor for step-down applications. The

sensed inductor current limit is set to 150mV across the

SENSE inputs.

SENSE+ (Pin 10):

The SENSE+ pin is the positive input for

the current sense ampliﬁer and is connected to the induc-

tor side of the sense resistor for step-down applications.

The sensed inductor current limit is set to 150mV across

the SENSE inputs.

PGND (Pin 11): The PGND pin is the high-current ground

reference for internal low side switch and the VCC regulator

circuit. Connect the pin directly to the negative terminal of

the VCC decoupling capacitor. See the Application Informa-

tion section for helpful hints on PCB layout of grounds.

LT3724MPFE Scheda tecnica(PDF) 6 Page - Linear Technology

LT3724MPFE Scheda tecnica(HTML) 6 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Scheda tecnica Scarica

Link URL