November 2006

PCS5I9351

rev 0.3

2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer

7 of 13

Notice: The information in this document is subject to change without notice.

1

Parameter

Description

Condition

Min

Typ

Max

Unit

VCO Frequency

200

500

MHz

÷2 Feedback

100

200

÷4 Feedback

50

125

÷8 Feedback

25

62.5

Input Frequency

Bypass mode

(PLL_EN = 0)

0

200

MHz

Input Duty Cycle

25

75

%

Peak-Peak Input Voltage

LVPECL

500

1000

mV

Common Mode Range

2

LVPECL

1.2

V

TCLK Input Rise/FallTime

0.8V to 2.0V

1.0

nS

÷2 Output

100

200

÷4 Output

50

125

Maximum Output Frequency

÷8 Output

25

62.5

MHz

47.5

52.5

DC

Output Duty Cycle

45

55

%

Output Rise/Fall times

0.8V to 2.4V

0.1

1.0

nS

TCLK to FB_IN, same VDD

-100

100

Propagation Delay

(static phase offset)

PCLK to FB_IN, same VDD

-100

100

pS

Output-to-Output Skew

Banks at same voltage

150

pS

Bank-to-Bank Skew

Banks at different voltages

350

pS

Output Disable Time

10

nS

Output Enable Time

10

nS

÷2 Feedback

2.2

÷4 Feedback

0.85

BW

PLL Closed Loop Bandwidth

(–3dB)

÷8 Feedback

0.6

MHz

Same frequency

150

Cycle-to-Cycle Jitter

Multiple frequencies

250

pS

Same frequency

100

Period Jitter

Multiple frequencies

150

pS

I/O Phase Jitter

175

pS

Maximum PLL Lock Time

1

mS