November 2006

PCS5I9351

rev 0.3

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200, Campbell, CA 95008

• Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

Notice: The information in this document is subject to change without notice.

2.5V or 3.3V, 200MHz, 9-Output Zero Delay Buffer

Features

•

Output frequency range: 25MHz to 200MHz

•

Input frequency range: 25MHz to 200MHz

•

2.5V or 3.3V operation

•

Split 2.5V/3.3V outputs

•

± 2.5% max Output duty cycle variation

•

Nine Clock outputs: Drive up to 18 clock lines

•

Two reference clock inputs: LVPECL or LVCMOS

•

150-pS max output-output skew

•

Phase-locked loop (PLL) bypass mode

•

‘SpreadTrak’

•

Output enable/disable

•

Pin-compatible with MPC9351 and CY29351.

•

Industrial temperature range: -40°C to +85°C

•

32-pin 1.0mm TQFP & LQFP Packages.

Functional Description

The PCS5I9351 is a low

voltage high performance

200MHz PLL-based zero delay buffer designed for high

speed clock distribution applications.

The PCS5I9351 features LVPECL and LVCMOS reference

clock inputs and provides 9 outputs partitioned in 4 banks

of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by

2 or 4 while the other banks divide by 4 or 8 per SEL(A:D)

settings, see Table.2. These dividers allow output to input

ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each LVCMOS

compatible output can drive 50Ω series or parallel

terminated transmission lines. For series terminated

transmission lines, each output can drive one or two traces

giving the device an effective fanout of 1:18.

The PLL is ensured stable given that the VCO is configured

to run between 200MHz to 500MHz. This allows a wide

range of output frequencies from 25MHz to 200MHz. For

normal operation, the external feedback input, FB_IN, is

connected to one of the outputs. The internal VCO is

running at multiples of the input reference clock set by the

feedback divider, see the Table 1.

When PLL_EN is LOW, PLL is bypassed and the reference

clock directly feeds the output dividers. This mode is fully

static and the minimum input clock frequency specification

does not apply.