TMC2192 datasheet(3/69 Pages) CADEKA

3 / 69 page

PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

List of Figures

Figure 1.

Input Formats . . . . . . . . . . . . . . . . . . . . . .7

Figure 2.

24 bit Input Format . . . . . . . . . . . . . . . . . .7

Figure 3.

CCIR656 Input Format . . . . . . . . . . . . . . .8

Figure 4.

10 bit Input Format . . . . . . . . . . . . . . . . . .8

Figure 5.

20 bit 4:2:2 Input Format . . . . . . . . . . . . .8

Figure 6.

20 bit 4:4:4 Input Format . . . . . . . . . . . . .8

Figure 7.

Propagation Delay through the

Encoder . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 8.

Horizontal Timing . . . . . . . . . . . . . . . . . .13

Figure 9.

Horizontal Timing – Vertical Blanking . . .13

Figure 10. Horizontal Timing – 1st Half-line. . . . . . .14

Figure 11. Horizontal Timing – 2nd Half-line . . . . . .14

Figure 12. NTSC Vertical Interval . . . . . . . . . . . . . .15

Figure 13. PAL Vertical Interval . . . . . . . . . . . . . . . .17

Figure 14. PAL-M Vertical Interval . . . . . . . . . . . . . .19

Figure 15. Burst Envelope . . . . . . . . . . . . . . . . . . . .23

Figure 16. Gaussian Filter Response . . . . . . . . . . .23

Figure 17. Interpolation Filter. . . . . . . . . . . . . . . . . .25

Figure 18. Interpolation Filter – Passband

Detail . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 19. X/SIN(X) Filter . . . . . . . . . . . . . . . . . . . .25

Figure 20. Layering Engine . . . . . . . . . . . . . . . . . . .28

Figure 21. Overlay Outputs . . . . . . . . . . . . . . . . . . .29

Figure 22. Data Keying . . . . . . . . . . . . . . . . . . . . . .29

Figure 23. Microprocessor Parallel Port –

Write Timing . . . . . . . . . . . . . . . . . . . . . .30

Figure 24. Microprocessor Parallel Port –

Read Timing . . . . . . . . . . . . . . . . . . . . . .30

Figure 25. Serial Port Read/Write Timing . . . . . . . .31

Figure 26. Serial Interface – Typical Byte

Transfer. . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 27. Serial Interface – Chip Address . . . . . . .32

Figure 28. Typical Analog Reconstruction Filter . . .63

Figure 29. Overall Response . . . . . . . . . . . . . . . . . .63

Figure 30. Typical Layout . . . . . . . . . . . . . . . . . . . . .65

Figure 31. ST-163E Layout . . . . . . . . . . . . . . . . . . .66

Figure 32. Pass Band . . . . . . . . . . . . . . . . . . . . . . .67

Figure 33. Stop Band. . . . . . . . . . . . . . . . . . . . . . . .67

Figure 34. 2T Pulse . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 35. Group Delay . . . . . . . . . . . . . . . . . . . . . .67

List of Tables

Table 1.

CSM Coefﬁcient Range . . . . . . . . . . . . . 9

Table 2.

Expected Output Values for the

CSM with YCBCR Inputs . . . . . . . . . . . . 9

Table 3.

PDC Edge Control . . . . . . . . . . . . . . . . 11

Table 4.

Horizontal Line Equations. . . . . . . . . . . 12

Table 5.

Horizontal Timing Speciﬁcations. . . . . . 13

Table 6.

Vertical Interval Timing

Speciﬁcations . . . . . . . . . . . . . . . . . . . . 14

Table 7.

Default Horizontal Timing

Parameters . . . . . . . . . . . . . . . . . . . . . . 15

Table 8.

NTSC Field/Line Sequence and

Identiﬁcation . . . . . . . . . . . . . . . . . . . . . 16

Table 9.

PAL Field/Line Sequence and

Identiﬁcation . . . . . . . . . . . . . . . . . . . . . 18

Table 10.

PAL-M Field/Line Sequence and

Identiﬁcation . . . . . . . . . . . . . . . . . . . . . 20

Table 11.

Standard Subcarrier Parameters . . . . . 22

Table 12.

Line by Line Pedestal Enable . . . . . . . . 23

Table 13.

Closed Caption Line Selection . . . . . . . 24

Table 14.

D/A Outputs . . . . . . . . . . . . . . . . . . . . . 25

Table 15.

Ancillary Data Format . . . . . . . . . . . . . . 26

Table 16.

Ancillary Data Control – Phase . . . . . . 27

Table 17.

Ancillary Data Control Frequency. . . . . 27

Table 18.

Field Identiﬁcation and Subcarrier

Reset Modes . . . . . . . . . . . . . . . . . . . . 27

Table 19.

Layering and Keying Modes . . . . . . . . . 28

Table 20.

Overlay Address Map . . . . . . . . . . . . . . 29

Table 21.

Parallel Port Control . . . . . . . . . . . . . . . 30

Table 22.

Serial Port Addresses. . . . . . . . . . . . . . 31

Table 23.

Control Register Map . . . . . . . . . . . . . . 33

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