TMC2193KJC datasheet(45/72 Pages) CADEKA

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PRODUCT SPECIFICATION

TMC2193

REV. 1.0 3/26/03

Control Register Deﬁnitions (continued)

DAC Control Register (0x10)

76543210

DAC4DIS

DAC3DIS

DAC2DIS

DAC1DIS

Reserved

OLUTDIS

OUTMODE

Reg

Bit

Name

Description

DAC4DIS

D/A #4 Disable.

When DAC4DIS is LOW, the COMPOSITE D/A is enabled.

When DAC4DIS is HIGH, the COMPOSITE D/A is disabled.

DAC3DIS

D/A #3 Disable.

When DAC3DIS is LOW, the CHROMA /PR/R D/A is enabled.

When DAC3DIS is HIGH, the CHROMA /PR/R D/A is disabled.

DAC2DIS

D/A #2 Disable.

When DAC2DIS is LOW, the LUMA/PB/B D/A is enabled.

When DAC2DIS is HIGH, the LUMA/PB/B D/A is disabled.

DAC1DIS

D/A #1 Disable.

When DAC1DIS is LOW, the COMP/Y/G and reference D/A is enabled.

When DAC1DIS is HIGH, the COMP/Y/G and reference D/A is disabled.

Reserved

Set to 0.

OLUTDIS

Overlay LUT Disable.

When OLUTDIS is LOW, the olut is enabled.

When OLUTDIS is HIGH, the olut is disabled.

1-0

OUTMODE

Output Modes.

Bit[1:0]

DAC1

DAC2

DAC3

DAC4

Comp2

Comp1

Comp2

10 (ext. sync)

Green

Blue

Red

Comp2

11 (sync on G)

Green

Blue

Red

Comp2

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