TMC2193KJC datasheet(48/72 Pages) CADEKA

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TMC2193

PRODUCT SPECIFICATION

REV. 1.0 3/26/03

Control Register Deﬁnitions (continued)

VBI Ped Enable Register (0x17)

76543210

VBIPEDOL

HVA

Reg

Bit

Name

Description

7-1

VBIPEDOM

VBI Pedestal Enable, Odd Fields.

VBIPEDOL is the bits 6-0 of VBIPEDO[14:0]. VBIPEDO controls the

addition of pedestal on a line by line basis from line 273 (VBIPEDE[0] =

HIGH) to line 286 (VBIPEDE[13] = HIGH) in the ODD field of NTSC.

VBIPEDO[14] controls the pedestal from line 287 to line 525 inclusive.

HVA

Horizontal and Vertical Sync Alignment.

When HVA is LOW, the falling edge of HSIN and VSIN must occur just prior

to the rising edge of PXCK to start an field 1. When HVA is HIGH, VSIN is

allowed to vary from HSIN by

±32 pixels.

Vertical Blanking Interval Enable Register (0x18)

76543210

Reserved

GLKCTL1

GLKCTL0

VBIENF1

Reg

Bit

Name

Description

Reserved

GLKCTL1

Genlock Control Register 1.

When GLKCTL1 is LOW, the PALODD bit of the GRS stream is ignored.

When GLKCTL1 is HIGH, the PALODD bit of the GRS stream controls the

PALODD flip of the subcarrier.

GLKCTL0

Genlock Control Register 0.

When GLKCTL0 is LOW, the Color Frame bit of the GRS stream is ignored.

When GLKCTL0 is HIGH, the Color Frame bit of the GRS stream controls

the field sequence in the FVHGEN.

4-0

VBIENF

VBI Active Video Enable, Field 1.

The value of VBIENF1 determines which line blanking stops and active line

for EVEN fields in NTSC starting from line 4 to line 35 or an ODD fields for

PAL starting from line 1 to line 32.

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