AS4DDR232M72PBG-3SLASHIT datasheet(10/28 Pages) AUSTIN

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2.4 G

2.4 Gbbbbb SDRAM-DDR2

SDRAM-DDR2

AS4DDR232M72PBG

Rev. 2.0 5/07

Austin Semiconductor, Inc. ● Austin, Texas ● 512.339.1188 ● www.austinsemiconductor.com

Austin Semiconductor, Inc.

CAS LATENCY (CL)

The CAS latency (CL) is defined by bits M4-M6, as shown

in Figure 5. CL is the delay, in clock cycles, between the

registration of a READ command and the availability of the

first bit of output data. The CL can be set to 3, 4, 5, or 6

clocks, depending on the speed grade option being used.

DDR2 SDRAM does not support any half-clock latencies.

Reserved states should not be used as unknown operation

or incompatibility with future versions may result.

DDR2 SDRAM also supports a feature called posted CAS

additive latency (AL). This feature allows the READ command

to be issued prior to tRCD (MIN) by delaying the

internal command to the DDR2 SDRAM by AL clocks.

Examples of CL = 3 and CL = 4 are shown in Figure 6; both

assume AL = 0. If a READ command is registered at clock

edge n, and the CL is m clocks, the data will be available

nominally coincident with clock edge n+m (this assumes

AL = 0).

FIGURE 6 - CAS LATENCY (CL)

CK#

COMMAND

DQS, DQS#

CK#

COMMAND

DQS, DQS#

Burst length = 4

Posted CAS# additive latency (AL) = 0

Shown with nominal

t AC, tDQSCK, and tDQSQ

DOUT

n + 3

DOUT

n + 2

DOUT

n + 1

CL = 3 (AL = 0)

READ

NOP

DOUT

NOP

DOUT

n + 3

DOUT

n + 2

DOUT

n + 1

CL = 4 (AL = 0)

READ

NOP

DOUT

NOP

TRANSITIONING DATA

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