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AD8465WBCPZ-R7 Scheda tecnica(PDF) 12 Page - Analog Devices |
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AD8465WBCPZ-R7 Scheda tecnica(HTML) 12 Page - Analog Devices |
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12 / 16 page ![]() AD8465 Rev. 0 | Page 12 of 16 CROSSOVER BIAS POINTS The AD8465 comparator offers a programmable hysteresis feature that significantly improves accuracy and stability. Connecting an external pull-down resistor or a current source from the LE/HYS pin to GND varies the amount of hysteresis in a predictable and stable manner. Leaving the LE/HYS pin disconnected or driving it high removes hysteresis. The maxi- mum hysteresis that can be applied using this pin is approximately 160 mV. Figure 19 illustrates the amount of hysteresis applied as a function of external resistor value. Figure 10 illustrates hysteresis as a function of current. Rail-to-rail inputs of this type, in both op amps and comparators, have a dual front-end design. Certain devices are active near the VCCI rail and others are active near the VEE rail. At some predeter- mined point in the common-mode range, a crossover occurs. At this point, normally VCCI/2, the direction of the bias current reverses and there are changes in measured offset voltages and currents. MINIMUM INPUT SLEW RATE REQUIREMENT With the rated load capacitance and normal good PCB design practice, as discussed in the Optimizing Performance section, these comparators should be stable at any input slew rate with no hysteresis. Broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. With additional capacitive loading or poor bypassing, oscillation is observed. This oscillation is due to the high gain bandwidth of the comparator in combina- tion with feedback parasitics in the package and PCB. In many applications, chattering is not harmful. The hysteresis control pin appears as a 1.25 V bias voltage seen through a series resistance of 70 kΩ ± 20% throughout the hysteresis control range. The advantages of applying hysteresis in this manner are improved accuracy, improved stability, reduced component count, and maximum versatility. An external bypass capacitor is not recommended on the LE/HYS pin because it would likely degrade the jitter performance of the device and impair the latch function. As described in the Using/Disabling the Latch Feature section, hysteresis control need not compro- mise the latch function. 0 50 100 150 200 250 50 100 150 200 250 300 350 400 450 500 HYSTERESIS RESISTOR (kΩ) VCC = 2.5V VCC = 5.5V Figure 19. Hysteresis vs. RHYS Control Resistor |
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