PCIMX515CJM6C datasheet(55/184 Pages) FREESCALE

Il numero della parte	PCIMX515CJM6C

Spiegazioni elettronici	i.MX51 Applications Processors for Consumer and Industrial Products

PDF	184 Pages

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Produttore elettronici	FREESCALE [Freescale Semiconductor, Inc]

Homepage	http://www.freescale.com

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Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Figure 31. Mobile DDR SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram

Table 44. Mobile DDR SDRAM Read Cycle Parameter Table1

1 Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for

address and controls

PARAMETER

Symbol

200 MHz2

2 SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal

value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK

and SDCLK (inverted clock)

166 MHz

133 MHz

Unit

Min Max Min Max Min Max

DD24 DQS - DQ Skew (defines the Data valid window in read cycles

related to DQS)

tDQSQ

—

0.4

—

0.75

—

0.85

DD25 DQS DQ in HOLD time from DQS

tQH

1.75

—

2.05

—

2.6

—

DD26 DQS output access time from SDCLK posedge

tDQSCK

5.5

6.5

SDCLK

SDCLK_B

DQS (input)

DQ (input)

Data

DD26

DD24

DD25

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