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PCIMX515CJM6C Scheda tecnica(PDF) 16 Page - Freescale Semiconductor, Inc |
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PCIMX515CJM6C Scheda tecnica(HTML) 16 Page - Freescale Semiconductor, Inc |
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16 / 184 page ![]() i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 16 Freescale Semiconductor Preliminary—Subject to Change Without Notice Electrical Characteristics Table 8. i.MX51 Operating Ranges Symbol Parameter Minimum1 Nominal2 Maximum1 Unit VDDGP MCIMX51xD products (Consumer) ARM core supply voltage 0 ≤ f ARM ≤ 167 MHz 0.8 0.85 1.15 V ARM core supply voltage 167 < f ARM ≤ 800 MHz 1.05 1.1 1.15 V ARM core supply voltage Stop mode 0.83 0.85 1.15 V VDDGP MCIMX51xC products (Industrial) ARM core supply voltage 0 < f ARM ≤ 600 MHz TBD 1.0 TBD V ARM core supply voltage Stop mode TBD 0.95 TBD V VCC MCIMX51xD products (Consumer) Peripheral supply voltage High Performance Mode (HPM) The clock frequencies are derived from AXI and AHB buses using 133 or 166 MHz (as needed). The DDR clock rate is 200 MHz. Note: For detailed information about the use of 133 or 166 MHz clocks, refer to the i.MX51 Reference Manual. 1.175 1.225 1.275 V Peripheral supply voltage Low Performance Mode (LPM) The clock frequencies are derived from AXI and AHB buses at 44 MHz and a DDR clock rate of DDR Clock/3. DDR2 does not support frequencies below 125 MHz per JEDEC. 1.00 1.05 1.275 V Peripheral supply voltage—Stop mode 0.93 0.95 1.275 V VCC MCIMX51xC products (Industrial) Peripheral supply voltage High Performance Mode (HPM) The clock frequencies are derived from AXI and AHB buses using 133 or 166 MHz (as needed). The DDR clock rate is 200 MHz. Note: For detailed information about the use of 133 or 166 MHz clocks, refer to the i.MX51 Reference Manual. TBD 1.225 TBD V Peripheral supply voltage—Stop mode TBD 0.95 TBD V VDDA Memory arrays voltage—Run Mode 1.15 1.20 1.275 V Memory arrays voltage—Stop Mode 0.93 0.95 1.275 V VDD_DIG_PLL_A VDD_DIG_PLL_B PLL Digital supplies 1.15 1.2 1.35 V VDD_ANA_PLL_A VDD_ANA_PLL_B PLL Analog supplies 1.75 1.8 1.95 V |
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