ICS1893CF datasheet(40/127 Pages) IDT

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ICS1893CF, Rev. J, 08/11/09

August, 2009

Chapter 6 Functional Blocks

ICS1893CF Data Sheet - Release

Note: The Management Frame Structure starts from and returns to an IDLE condition. However, the IDLE

periods are not part of the Management Frame Structure.

6.6.2.1 Management Frame Preamble

The ICS1893CF continually monitors its serial management interface for either valid data or a Management

Frame (MF) Preamble, based upon the setting of the MF Preamble Suppression bit, 1.6. When the MF

Preamble Suppression is disabled, an ICS1893CF waits for a MF Preamble which indicates the start of an

STA transaction. A Management Frame Preamble is a pattern of 32 contiguous logic one bits on the MDIO

pin, along with 32 corresponding clock cycles on the MDC pin.

The ICS1893CF supports the Management Frame (MF) Preamble Suppression capability on its

Management Interface, thereby providing a method to shorten the Management Frame and provide an STA

with faster access to the Management Registers.

The ability to process Management Frames that do not have a preamble is provided by the Management

Frame Preamble Suppression bit, (bit 1.6 in the ICS1893CF’s Status Register). This is an ISO/IEC defined

status bit that is intended to provide an indication of whether or not a PHY supports the MF Preamble

Suppression feature. In order to maintain backward compatibility with the ICS1890, which did not support

MF Preamble Suppression, the ICS1893CF MF Preamble Suppression bit is a Command Override Write

bit which defaults to a logic zero. An STA can enable MF Preamble Suppression by writing a logic one to bit

1.6 subsequent to a write of logic one to the Command Override bit, 16.15. For an explanation of the

Command Override Write bits, see Section 7.1.2, “Management Register Bit Access”.

6.6.2.2 Management Frame Start

A valid Management Frame includes a start-of-frame delimiter, SFD, immediately following the preamble.

The SFD bit pattern is 01b and is synchronous with two clock cycles on the MDC pin.

6.6.2.3 Management Frame Operation Code

A valid Management Frame includes an operation code (OP) immediately following the start-of-frame

delimiter. There are two valid operation codes: one for reading from a management register, 10b, and one

for writing to a management register, 01b. The ICS1893CF does not respond to the codes 00b and 11b,

which the ISO/IEC specification defines as invalid.

6.6.2.4 Management Frame PHY Address

The two-wire, Serial Management Interface is specified to allow busing (that is, the sharing of the two wires

among multiple PHYs). The Management Frame includes a 5-bit PHY Address field, PHYAD, allowing for

32 unique addresses. An STA uniquely identifies each of the PHYs that share a single serial management

interface by using this 5-bit PHY Address field, PHYAD.

Table 6-1. Management Frame Structure Summary

Frame Field

Data

Comment

Acronym

Frame Function

PRE

Preamble (Bit 1.6)

11..11

32 ones

SFD

Start of Frame

2 bits

Operation Code

10/01 (read/write)

2 bits

PHYAD

PHY Address (Bits 16.10:6)

AAAAA

5 bits

REGAD

RRRRR

5 bits

Turnaround

Z0/10 (read/write)

2 bits

DATA

Data

DDD..DD

16 bits

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