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ICS1893CF Scheda tecnica(PDF) 55 Page - Integrated Device Technology |
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ICS1893CF Scheda tecnica(HTML) 55 Page - Integrated Device Technology |
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55 / 127 page ![]() Chapter 7 Management Register Set ICS1893CF, Rev. J, 08/11/09 August, 2009 55 ICS1893CF Data Sheet Rev. J - Release Copyright © 2009, Integrated Device Technology, Inc. All rights reserved. 7.4 Register 2: PHY Identifier Register Table 7-7 lists the bits for PHY Identifier Register (Register 2), which is one of two PHY Identifier Registers that are part of a set defined by the ISO/IEC specification. As a set, the PHY Identifier Registers (Registers 2 and 3) include a unique, 32-bit PHY Identifier composed from the following: • Organizationally Unique Identifier (OUI), discussed in this section • Manufacturer’s PHY Model Number, discussed in Section 7.5, “Register 3: PHY Identifier Register” • Manufacturer’s PHY Revision Number, discussed in Section 7.5, “Register 3: PHY Identifier Register” All of the bits in the two PHY Identifier Registers are Command Override Write bits. An STA can read them at any time without condition. However, an STA can modify these register bits only when the Command Register Override bit (bit 16.15) is enabled with a logic one. Note: For an explanation of acronyms used in Table 7-5, see Chapter 1, “Abbreviations and Acronyms”. Table 7-7. PHY Identifier Register (Register 2 [0x02]) Bit Definition When Bit = 0 When Bit = 1 Access Special Function Default Hex 2.15 OUI bit 3 | c N/A N/A CW – 0 0 2.14 OUI bit 4 | d N/A N/A CW – 0 2.13 OUI bit 5 | e N/A N/A CW – 0 2.12 OUI bit 6 | f N/A N/A CW – 0 2.11 OUI bit 7 | g N/A N/A CW – 0 0 2.10 OUI bit 8 | h N/A N/A CW – 0 2.9 OUI bit 9 | I N/A N/A CW – 0 2.8 OUI bit 10 | j N/A N/A CW – 0 2.7 OUI bit 11 | k N/A N/A CW – 0 1 2.6 OUI bit 12 | l N/A N/A CW – 0 2.5 OUI bit 13 | m N/A N/A CW – 0 2.4 OUI bit 14 | n N/A N/A CW – 1 2.3 OUI bit 15 | o N/A N/A CW – 0 5 2.2 OUI bit 16 | p N/A N/A CW – 1 2.1 OUI bit 17 | q N/A N/A CW – 0 2.0 OUI bit 18 | r N/A N/A CW – 1 |
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