AT89LP428 datasheet(82/149 Pages) ATMEL

82 / 149 page

3654A–MICRO–8/09

AT89LP428/828

Reception is initiated by the condition REN = 1 and R1 = 0. At the next clock cycle, the RX Con-

trol unit writes the bits 11111110 to the receive shift register and activates RECEIVE in the next

clock phase. RECEIVE enables Shift Clock to alternate output function line of P3.1. As data bits

come in from the right, “1”s shift out to the left. When the “0” that was initially loaded into the

right-most position arrives at the left-most position in the shift register, it flags the RX Control

block to do one last shift and load SBUF. Then RECEIVE is cleared and RI is set.

The relationship between the shift clock and data is determined by the combination of the SM2

and SMOD1 bits as listed in Table 16-5 and shown in Figure 16-2. The SM2 bit determines the

idle state of the clock when not currently transmitting/receiving. The SMOD1 bit determines if the

output data is stable for both edges of the clock, or just one.

Table 16-5.

Mode 0 Clock and Data Modes

SM2

SMOD1

Clock Idle

Data Changed

Data Sampled

High

While clock is high

Positive edge of clock

High

Negative edge of clock

Positive edge of clock

Low

While clock is low

Negative edge of clock

Low

Negative edge of clock

Positive edge of clock

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