M306S0FADGP datasheet(97/208 Pages) RENESAS

97 / 208 page

Rev.5.01

Dec 10, 2009

page 97 of 201

REJ03B0014-0501

M16C/6S Group

UARTi transmit/receive control register 1 (i=0, 1)

Symbol

Address

After reset

U0C1, U1C1

03A516,03AD16

000000102

Bit name

Bit

symbol

Function

Transmit enable bit

Receive enable bit

Receive complete flag

Transmit buffer

empty flag

0 : Transmission disabled

1 : Transmission enabled

0 : Data present in UiTB register

1 : No data present in UiTB register

0 : Reception disabled

1 : Reception enabled

0 : No data present in UiRB register

1 : Data present in UiRB register

Nothing is assigned.

When write, set “0”. When read, these contents are “0”.

UART2 transmit/receive control register 1

Symbol

Address

After reset

U2C1

037D16

000000102

Bit name

Bit

symbol

Function

Transmit enable bit

Receive enable bit

Receive complete flag

Transmit buffer

empty flag

0 : Transmission disabled

1 : Transmission enabled

0 : Reception disabled

1 : Reception enabled

U2IRS UART2 transmit interrupt

cause select bit

0 : Transmit buffer empty (TI = 1)

1 : Transmit is completed (TXEPT = 1)

U2RRM UART2 continuous

receive mode enable bit

0 : Continuous receive mode disabled

1 : Continuous receive mode enabled

Data logic select bit

0 : No reverse

1 : Reverse

U2LCH

U2ERE Error signal output

enable bit

0 : Output disabled

1 : Output enabled

Data logic select bit

0 : No reverse

1 : Reverse

UiLCH

UiERE

Error signal output

enable bit

0 : Output disabled

1 : Output enabled

(b5-b4)

0 : Data present in U2TB register

1 : No data present in U2TB register

0 : No data present in U2RB register

1 : Data present in U2RB register

NOTES:

1. The UiLCH bit is enabled when the SMD2 to SMD0 bits in the UiMR register are set to “001b” (clock synchronous serial I/O

mode), “100b” (UART mode, 7-bit transfer data), or “101b” (UART mode, 8-bit transfer data).

Set this bit to “0” when the SMD2 to SMD0 bits are set to “010b” (I2C mode) or “110b” (UART mode, 9-bit transfer data).

NOTES:

1. The U2LCH bit is enabled when the SMD2 to SMD0 bits in the U2MR registerare set to “001b” (clock synchronous serial I/O

mode), “100b” (UART mode, 7-bit transfer data), or “101b” (UART mode, 8-bit transfer data).

Set this bit to “0” when the SMD2 to SMD0 bits are set to “010b” (I2C mode) or “110b” (UART mode, 9-bit transfer data).

Figure 1.13.5. U0C1 to U2C1 Registers

Serial I/O

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