R5F363AMNFB datasheet(24/115 Pages) RENESAS

24 / 115 page

REJ03B0271-0100 Rev.1.00 Sep 15, 2009

Page 24 of 113

M16C/63 Group

2. Central Processing Unit (CPU)

2.2

Address Registers (A0 and A1)

A0 and A1 are 16-bit registers used for indirect addressing, relative addressing, transfer, arithmetic, and

logic operations. A0 can be combined with A1 and used as a 32-bit address register (A1A0).

2.3

Frame Base Register (FB)

FB is a 16-bit register that is used for FB relative addressing.

2.4

Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table.

2.5

Program Counter (PC)

The PC is 20 bits wide and indicates the address of the next instruction to be executed.

2.6

User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The USP and ISP stack pointers (SP) are each comprised of 16 bits. The U flag is used to switch between

USP and ISP.

2.7

Static Base Register (SB)

SB is a 16-bit register used for SB relative addressing.

2.8

Flag Register (FLG)

FLG is an 11-bit register that indicates the CPU state.

2.8.1

Carry Flag (C Flag)

The C flag retains a carry, borrow, or shift-out bit generated by the arithmetic/logic unit.

2.8.2

Debug Flag (D Flag)

The D flag is for debugging only. Set it to 0.

2.8.3

Zero Flag (Z Flag)

The Z flag becomes 1 when an arithmetic operation results in 0. Otherwise, it becomes 0.

2.8.4

Sign Flag (S Flag)

The S flag becomes 1 when an arithmetic operation results in a negative value. Otherwise, it becomes

2.8.5

2.8.6

Overflow Flag (O Flag)

The O flag becomes 1 when an arithmetic operation results in an overflow. Otherwise, it becomes 0.

2.8.7

Interrupt Enable Flag (I Flag)

The I flag enables maskable interrupts.

Maskable interrupts are disabled when the I flag is 0, and enabled when it is 1. The I flag becomes 0

when an interrupt request is accepted.

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