Pad Coordinates

Unit:

mm

Pad No.

X

Y

Pad No.

X

Y

1

-802.951

939.295

25

925.915

-338.315

2

-927.055

343.250

26

925.915

-239.255

3

-927.055

244.230

27

925.915

-140.195

4

-927.055

89.374

28

925.915

-41.134

5

-925.358

-52.510

29

925.915

57.925

6

-925.358

-151.360

30

925.915

156.986

7

-925.785

-566.516

31

925.915

256.046

8

-925.785

-675.287

32

925.915

355.106

9

-925.699

-773.697

33

849.589

939.295

10

-896.840

-939.537

34

750.530

939.295

11

-637.515

-935.685

35

651.469

939.295

12

-452.726

-935.685

36

552.409

939.295

13

-288.935

-935.685

37

453.349

939.295

14

-189.915

-935.685

38

354.289

939.295

15

-84.350

-935.685

39

255.230

939.295

16

14.669

-935.685

40

156.169

939.295

17

114.260

-940.130

41

57.109

939.295

18

213.320

-940.130

42

-41.951

939.295

19

312.380

-940.130

43

-141.010

939.295

20

925.915

-867.615

44

-240.070

939.295

21

925.915

-768.555

45

-339.130

939.295

22

925.915

-669.495

46

-438.190

939.295

23

925.915

-570.435

47

-537.250

939.295

24

925.915

-437.375

48

-636.310

939.295

Pad Description

Pad No.

Pad Name

I/O

Function

1CS

I

Chip selection input with pull-high resistor

When the CS is logic high, the data and command read from or written to

the HT1621 are disabled. The serial interface circuit is also reset. But if CS

is at logic low level and is input to the CS pad, the data and command trans-

mission between the host controller and the HT1621 are all enabled.

2RD

I

READ clock input with pull-high resistor

Data in the RAM of the HT1621 are clocked out on the falling edge of the RD

signal. The clocked out data will appear on the DATA line. The host control-

ler can use the next rising edge to latch the clocked out data.

3WR

I

WRITE clock input with pull-high resistor

Data on the DATA line are latched into the HT1621 on the rising edge of the

WR signal.

4

DATA

I/O

Serial data input/output with pull-high resistor

5

VSS

¾

Negative power supply, ground

7

OSCI

I

The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to

generate a system clock. If the system clock comes from an external clock

source, the external clock source should be connected to the OSCI pad. But

if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads

can be left open.

6

OSCO

O

8

VLCD

I

LCD power input

9

VDD

¾

Positive power supply

10

IRQ

O

Time base or WDT overflow flag, NMOS open drain output

11, 12

BZ, BZ

O

2kHz or 4kHz tone frequency output pair

13~16

COM0~COM3

O

LCD common outputs

48~17

SEG0~SEG31

O

LCD segment outputs

HT1621

Rev. 2.60

4

October 28, 2009

PATENTED