MPC8535ECVTATH datasheet(25/126 Pages) FREESCALE

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Power Sequencing

MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

2.1.3

Output Driver Characteristics

Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates.

2.2

Power Sequencing

The MPC8535E requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These

requirements are as follows for power up:

VDD_PLAT, VDD_CORE (if POWER_EN is not used to control VDD_CORE), AVDD, BVDD, LVDD, OVDD,

SVDD,S2VDD, TVDD, XVDD and X2VDD

[Wait for POWER_EN to assert], then VDD_CORE (if POWER_EN is used to control VDD_CORE)

GVDD

All supplies must be at their stable values within 50 ms.

Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered

sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step

reach 10% of theirs.

In order to guarantee MCKE low during power-up, the above sequencing for GVDD is required. If there is no concern about any

of the DDR signals being in an indeterminate state during power-up, then the sequencing for GVDD is not required.

From a system standpoint, if any of the I/O power supplies ramp prior to the VDD platform supply, the I/Os associated with

that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the device.

During the Deep Sleep state, the VDD core supply is removed. But all other power supplies remain applied. Therefore, there is

no requirement to apply the VDD core supply before any other power rails when the silicon waking from Deep Sleep.

Table 4. Output Drive Capability

Driver Type

Programmable

Output Impedance

(

Ω)

Supply

Voltage

Notes

Local bus interface utilities signals

BVDD = 3.3 V

BVDD = 2.5 V

45(default)

125

BVDD = 3.3 V

BVDD = 2.5 V

BVDD = 1.8 V

PCI signals

OVDD = 3.3 V

42 (default)

DDR2 signal

32 (half strength mode)

GVDD = 1.8 V

DDR3 signal

40 (half strength mode)

GVDD = 1.5 V

TSEC signals

LVDD = 2.5/3.3 V

—

DUART, system control, JTAG

OVDD = 3.3 V

—

I2C

150

OVDD = 3.3 V

—

Notes:

1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.

2. The drive strength of the PCI interface is determined by the setting of the PCI1_GNT1 signal at reset.

3. The drive strength of the DDR2 or DDR3 interface in half-strength mode is at Tj = 105°C and at GVDD (min)

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