AS8218 datasheet(84/123 Pages) AMSCO

84 / 123 page

Data Sheet AS8218 / AS8228

Revision 3.0, 31-May-06

Page 84 of 123

Interrupt Priorities

Each interrupt source can be individually assigned one of two priority levels. A low priority interrupt can always

be interrupted by a higher-priority interrupt, but not by another low priority interrupt. A high-priority interrupt

cannot be interrupted by any other interrupt source.

If the corresponding IP bit is set then this interrupt is serviced first if another interrupt request occurs at the

same time where the IP bit is zero.

Interrupt on the same priority level are serviced due to the internal polling sequence starting with DSP highest

down to RTC lowest.

Symbol

Position

Function

Source Flags

IP.7

PRTC

IP.6

Real time clock, priority bit

TSA, STF, A1F, A2F

PS2

IP.5

UART2 serial port, priority bit

RI, TI

IP.4

UART1 serial port, priority bit

RI, TI

PSPI

IP.3

SPI serial port, priority bit

ITRA

PIOX

IP.2

MPIO external pin, priority bit

in Status 0 / Status 1

PT0

IP.1

Timer 0, priority bit

TF0

PDSP

IP.0

DSP priority bit

dai, alarm

Note:

1) Standard 8051 bits

PSPI

IP = 1

IP = 0

High

Priority

Interrupt

Low

Priority

Interrupt

IE Register

IP Register

Priority Level

High

Priority

Level

Low

Polling

Sequence

Global enable

Individual enables

Source

PIOX

PTO

PDSP

PS2

PRTC

Figure 22: Interrupt control system

AS8218 Scheda tecnica(PDF) 84 Page - ams AG

AS8218 Scheda tecnica(HTML) 84 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL