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DM9013EP Scheda tecnica(PDF) 21 Page - Davicom Semiconductor, Inc.

Il numero della parte DM9013EP
Spiegazioni elettronici  10/100 Mbps 3-port Ethernet Switch Controller with General Processor Interface
PDF  75 Pages
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Produttore elettronici  DAVICOM [Davicom Semiconductor, Inc.]
Homepage  http://www.davicom.com.tw
Logo DAVICOM - Davicom Semiconductor, Inc.

DM9013EP Scheda tecnica(HTML) 21 Page - Davicom Semiconductor, Inc.

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DM9013
3-port switch with Processor Interface
Preliminary datasheet
21
DM9013-15-DS-P03
April 9, 2009
6.1 Network Control Register (00H)
Bit
Name
Default
Description
7
RESERVED
0,RO
Reserved
6
RESERVED
P0,WO
Reserved
5
CLR1
PH0,RW
0: REG. 01H auto-cleared after read
1: REG. 01H cleared by writing 1 to respected bit.
4:2
RESERVED
0,RO
Reserved
1
LBK
PH0,
RW
Loopback test Mode
0
RST
PH0,RW
Software reset and auto clear after 10us
6.2 Network Status Register (01H)
Bit
Name
Default
Description
7:6
RESERVED
0,RO
Reserved
5
RESERVED
PH0,
Reserved
4
RESERVED
0,RO
Reserved
3
TX2END
PHS0,
RW/C1
TX Packet 2 Complete Status.
This bit is set after transmit completion of packet index 2
If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by
read or write 1.
2
TX1END
PHS0,
RW/C1
TX Packet 1 Complete status.
This bit is set after transmit completion of packet index 1
If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by
read or write 1.
1:0
RESERVED
0,RO
Reserved
6.3 TX Control Register (02H)
Bit
Name
Default
Description
7:4
RESERVED
0,RO
Reserved
3
CRC_DIS2
PHS0,RW CRC Appends Disable for Packet Index 2
2
RESERVED
0,RO
Reserved
1
CRC_DIS1
PHS0,RW CRC Appends Disable for Packet Index 1
0
TXREQ
PHS0,RW TX Request. Auto clears after transmit completely
6.4 RX Control Register (05H)
Bit
Name
Default
Description
7
HASHALL
PHS0,RW
Filter All address in Hash Table
6
RESERVED PHS0,RW
Reserved
5
RESERVED PHS0,RW
Reserved
4
RESERVED PHS0,RW
Reserved
3
ALL
PHS0,RW
Pass All Multicast Packets
2
RESERVED PHS0,RW
Reserved
1
PRMSC
PHS0,RW
Promiscuous Mode
0
RXEN
PHS0,RW
RX Enable



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