DM9102DEP datasheet(28/70 Pages) DAVICOM

28 / 70 page

Final

Version: DM9102D-DS-F01

May 10, 2006

RXWTE

0,RW

Receive Watchdog Timer Expired Enable

When this bit and CR7<15>, (CR5<9> are set together, it enable the interrupt of the

condition of the receive watchdog timer expired.

RXPSE

0,RW

Receive Process Stopped Enable

When set together with CR7<15> and CR5<8>. This bit is set to enable the

interrupt of receive process stopped condition.

RXDUE

0,RW

Receive Buffer Unavailable Enable

When this bit and CR7<15>, CR5<7> are set together, it will enable the interrupt of

receive buffer unavailable condition.

RXCIE

0,RW

Receive Complete Interrupt Enable

When this bit and CR7<16>, CR5<6> are set together, it will enable the interrupt of

receive process complete condition.

TXFUE

0,RW

Transmit FIFO Underrun Enable

When set together with CR7<15>, CR5<5>, it will enable the interrupt of transmit

FIFO underrun condition.

Reserved

0,RO

Reserved

TXJTE

0,RW

Transmit Jabber Expired Enable

When this bit and CR7<15>, CR5<3> are set together, it enables the interrupt of

transmit Jabber Timer Expired condition.

TXDUE

0,RW

Transmit Buffer Unavailable Enable

When this bit and CR7<16>, CR5<2> are set together, the interrupt of transmit

buffer unavailable is enabled.

TXPSE

0,RW

Transmit Process Stopped Enable

When this bit is set together with CR7<15> and CR5<1>, it will enable the interrupt

of the transmit process to stop.

TXCIE

0,RW

Transmit Complete Interrupt Enable

When this bit and CR7<16>, CR5<0> are set, the transmit interrupt is enabled.

6.2.9 Statistical Counter Register (CR8)

Bit

Name

Default

Description

ROCO

0,RO/C

Receive Overflow Counter Overflow

This bit is set when the Purged Packet Counter (RXDU) has an overflow condition.

30:25

Reserved

0,RO

Reserved

24:17

RXDU

0,RO/C

Receive Purged Packet Counter

This is a statistic counter to indicate the purged received packet counts upon FIFO

overflow.

RXPS

0,RO/C

Receive Missed Counter Overflow

This bit is set when the Receive Missed Frame Counter (RXCI) has an overflow

condition.

15:7

Reserved

0,RO

Reserved

6:0

RXCI

0,RO/C

Receive Missed Frame Counter

This is a statistic counter to indicate the Receive Missed Frame Count when there

is a host buffer unavailable condition for receive process.

6.2.10 Management Access Register (CR9)

31 30 29 28 27 26 25 24 23 22 21 20 19 18

17 16 15 14 13 12 11 10

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