WM8148

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 4.0 April 1999

9

RESET LEVEL CLAMP

MCLK

VSMP

RLC = 1

RLC = 0

t

RLCSU

t

RLCH

Figure 3 Reset Level Clamp Control Timing

CL

CL

CL

CL

MCLK

MODE 8-13

SMALL = 0

MODE 8-13

SMALL = 1

MODE 0-5

SMALL = 0

MODE 0-5

SMALL = 1

OFF

O N

OFF

OFF

O N

OFF

OFF

O N

OFF

OFF

O N

OFF

t

PER

t

RLCPD

t

RLCPD

t

RLCPD

t

RLCPD

t

RLCPD

t

RLCPD

t

RLCPD

t

RLCPD

Figure 4 Internal Clamp Signal (CL) Timing

TEST CONDITIONS

°C, MCLK = 48MHz unless

otherwise stated (AVDD denotes the voltage applied to all AVDD pins).

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

MCLK period

20.8

ns

Propagation delay

15

ns

Set-up time

10

ns

Hold time

10

ns

Notes: 1.

Internal clamp signal (CL) timing may be relative to either the falling or rising edge of MCLK depending on the setting of

control bits RESREF[3:0].

2.

Parameters are measured at 50% of the rising/falling edge.