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WM8148 Scheda tecnica(PDF) 12 Page - Wolfson Microelectronics plc |
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WM8148 Scheda tecnica(HTML) 12 Page - Wolfson Microelectronics plc |
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12 / 43 page ![]() WM8148 Production Data WOLFSON MICROELECTRONICS LTD PD Rev 4.0 April 1999 12 PARALLEL INTERFACE STB DNA RNW D[11:4] Z Z DATA IN ADDRESS IN ADC DATA OUT ADC DATA OUT DATA OUT ADC DATA OUT t STB t ASU t AH t DSU t DH t STDO t STAO t ADLS t ADLH t ADHS t ADHH t OPD t OPZ Figure 8 Parallel Interface Timing TEST CONDITIONS AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70 °C, MCLK = 48MHz unless otherwise stated (AVDD denotes the voltage applied to all AVDD pins). PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS RNW Low to OP[11:4] Hi-Z. tOPZ 20 ns Address set-up time to STB Low tASU 10 ns DNA Low set-up time to STB Low tADLS 10 ns Strobe Low time tSTB 50 ns Address hold time from STB High tAH 10 ns DNA Low hold time from STB High tADLH 10 ns Data set-up time to STB Low tDSU 10 ns DNA High set-up time to STB Low tADHS 10 ns Data hold time from STB High tDH 10 ns Data High hold time from STB High tADHH 10 ns RNW High to OP[11:4] output tOPD 35 ns Data output propagation delay from STB Low tSTDO 35 ns ADC data out propagation delay from STB High tSTAO 35 ns Note: Parameters are measured at 50% of the rising/falling edge. |
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