PCF8562TTSLASH2 datasheet(21/36 Pages) NXP

21 / 36 page

PCF8562_4

Product data sheet

Rev. 04 — 18 March 2009

21 of 36

NXP Semiconductors

PCF8562

Universal LCD driver for low multiplex rates

7.16.6 Input ﬁlters

To enhance noise immunity in electrically adverse environments, RC low-pass ﬁlters are

provided on the SDA and SCL lines.

7.16.7 I2C-bus protocol

Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8562.

The least signiﬁcant bit of the slave address that a PCF8562 will respond to is deﬁned by

the level tied to its SA0 input. The PCF8562 is a write-only device and will not respond to

a read access.

The I2C-bus protocol is shown in Figure 15. The sequence is initiated with a START

condition (S) from the I2C-bus master which is followed by one of two possible PCF8562

slave addresses available. All PCF8562s whose SA0 inputs correspond to bit 0 of the

slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is

ignored by all PCF8562s whose SA0 inputs are set to the alternative level.

After an acknowledgement, one or more command bytes follow, that deﬁne the status of

each addressed PCF8562.

The last command byte sent is identiﬁed by resetting its most signiﬁcant bit, continuation

bit C, (see Figure 16). The command bytes are also acknowledged by all addressed

PCF8562s on the bus.

After the last command byte, one or more display data bytes may follow. Display data

bytes are stored in the display RAM at the address speciﬁed by the data pointer and the

subaddress counter. Both data pointer and subaddress counter are automatically

updated.

Fig 15. I2C-bus protocol

Fig 16. Format of command byte

mdb078

011100

0 A C

COMMAND

DISPLAY DATA

slave address

R/W

acknowledge by

all addressed

PCF8576Ds

acknowledge

by A0, A1 and A2

selected

PCF8576D only

1 byte

update data pointers

and if necessary,

subaddress counter

≥ 1 byte(s)

≥ 0 byte(s)

msa833

REST OF OPCODE

MSB

LSB

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