Clock Inputs

1000 W

~ 2.4 V

CLK

CLK

AVDD5

AVDD5

1000 W

GND

ADS5474

GND

GND

~ 2.5 nH Bond Wire

~ 2.5 nH Bond Wire

Parasitic

~0.2pF

Parasitic

~0.2pF

S0292-04

Internal

Clock

Buffer

~ 0.5pF

Package

~ 0.5pF

Package

~ 200fF

BondPad

~ 200fF

BondPad

CLK

ADS5474

CLK

SquareWaveor

SineWave

0.01 F

m

0.01 F

m

ClockAmplitude

V

-

PP

90

85

80

75

70

65

60

0

0.5

1.0

1.5

5.0

2.0

2.5

3.0

f =400MSPS

f

=230MHz

S

IN

3.5

4.0

4.5

SFDR(dBc)

SNR(dBFS)

ADS5474

The ADS5474 clock input can be driven with either a differential clock signal or a single-ended clock input. The

of a factor in performance as the analog input frequency increases. In low-input-frequency applications, where

jitter may not be a big concern, the use of a single-ended clock could save cost and board space without much

performance tradeoff. When clocked with this configuration, it is best to connect CLK to ground with a 0.01-

µF

capacitor, while CLK is ac-coupled with a 0.01-

µF capacitor to the clock source, as shown in Figure 41.

Figure 40. Clock Input Circuit

Figure 41. Single-Ended Clock

Figure 42. AC Performance versus Clock Level

Copyright © 2007–2008, Texas Instruments Incorporated

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Product Folder Link(s): ADS5474