ClockDutyCycle

%

-

90

85

70

65

60

55

50

20

30

40

50

80

60

70

80

75

f =400MSPS

ClockInput=3V

S

PP

f

=10MHz

IN

f

=70MHz

IN

f

=230MHz

IN

f

=300MHz

IN

SNR(dBc)= 20

LOG10(2

f

j

)

-

p ´

´

´

´

IN

TOTAL

(1)

j

=(j

+j

)

TOTAL

ADC

CLOCK

2

1/2

2

(2)

ADS5474

Figure 46. SFDR vs Clock Duty Cycle

The ADS5474 is capable of achieving 69.2 dBFS SNR at 350 MHz of analog input frequency. In order to achieve

the SNR at 350 MHz the clock source rms jitter must be at least 144 fsec in order for the total rms jitter to be 177

fsec. A summary of maximum recommended rms clock jitter as a function of analog input frequency is provided

in Table 2. The equations used to create the table are also presented.

Table 2. Recommended RMS Clock Jitter

INPUT FREQUENCY

MEASURED SNR

TOTAL JITTER

MAXIMUM CLOCK JITTER

(MHz)

(dBc)

(fsec rms)

(fsec rms)

30

69.3

1818

1816

70

69.1

798

791

130

69.1

429

417

230

68.8

251

229

350

68.2

177

144

450

67.4

151

110

750

65.6

111

42

1000

63.7

104

14

Equation 1 and Equation 2 are used to estimate the required clock source jitter.

where:

Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the

clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.

For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not

required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see

Application Note SLWA034, Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC

Copyright © 2007–2008, Texas Instruments Incorporated

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