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SC68C652B Scheda tecnica(PDF) 2 Page - NXP Semiconductors |
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SC68C652B Scheda tecnica(HTML) 2 Page - NXP Semiconductors |
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2 / 43 page ![]() SC68C652B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 2 November 2009 2 of 43 NXP Semiconductors SC68C652B Dual UART with 32-byte FIFOs and IrDA encoder/decoder I Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break) I Transmit, Receive, Line Status, and Data Set interrupts independently controlled I Fully programmable character formatting: N 5, 6, 7, or 8-bit characters N Even, odd, or no parity formats N 1, 11⁄2, or 2 stop bit generation N Baud generation (DC to 5 Mbit/s) I False start bit detection I Complete status reporting capabilities I 3-state output TTL drive capabilities for bidirectional data bus and control bus I Line break generation and detection I Internal diagnostic capabilities: N Loopback controls for communications link fault isolation I Prioritized interrupt system controls I Modem control functions (CTS, RTS, DSR, DTR, RI, and CD) 3. Ordering information Table 1. Ordering information Type number Package Name Description Version SC68C652BIB48 LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2 |
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