HT83F60 datasheet(29/62 Pages) HOLTEK

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HT83FXX

Rev. 1.30

June 7, 2010

2C Interface

The I

2C bus is a bidirectional 2-line communication inter-

face originally developed by Philips. The possibility of

transmitting and receiving data on only 2 lines offers

many new application possibilities for microcontroller

based applications.

· I2C Interface Operation

As the I

2C interface pins are pin-shared with segment

pins and with the SPI function pins, the I

2C interface

must first be enabled by selecting the correct configu-

ration option.

There are two lines associated with the I

2C bus, the

first is known as SDA and is the Serial Data line, the

second is known as SCL line and is the Serial Clock

line. As many devices may be connected together on

the same bus, their outputs are both open drain types.

For this reason it is necessary that external pull-high

resistors are connected to these outputs. Note that no

chip select line exists, as each device on the I

2C bus is

identified by a unique address which will be transmit-

ted and received on the I

2C bus.

When two devices communicate with each other on

the bidirectional I

2C bus, one is known as the master

device and one as the slave device. Both master and

slave can transmit and receive data, however, it is the

master device that has overall control of the bus. For

this device, which only operates in slave mode, there

are two methods of transferring data on the I

2C bus,

the slave transmit mode and the slave receive mode.

· I2C Registers

There are three control registers associated with the

2C bus, SIMC0, SIMC1 and SIMAR and one data reg-

ister, SIMDR.

The SIMDR register is used to store the data being

transmitted and received on the I

2C bus. Before the

microcontroller writes data to the I

2C bus, the actual

data to be transmitted must be placed in the SIMDR

2C bus,

the microcontroller can read it from the SIMDR regis-

ter. Any transmission of data to the I

2C bus or recep-

tion of data from the I

2C bus must be made via the

SIMDR register.

The SIMAR register is the location where the slave

address of the microcontroller is stored. Bits 1~7 of

the SIMAR register define the microcontroller slave

address. Bit 0 is not defined. When a master device,

which is connected to the I

2C bus, sends out an ad-

dress, which matches the slave address in the SIMAR

lected.

Note that the SIMAR register is the same register as

SIMC2 which is used by the SPI interface.

The SIMC0 register is used for the I

2C overall on/off

control.

· I2C Configuration Option

There are several configuration options associated

with the I

2C interface. One of these is to enable the

RNIC bit function which selects the RNIC bit in SIMC1

debounce time of the I

2C interface. This add a

debounce delay time to the external clock to reduce

the possibility of glitches on the clock line causing er-

roneous operation. The debounce time if selected can

be chosen to be either 1 or 2 system clocks.

S I M A R R e g i s t e r

b 7

N o t i m p l e m e n t e d , r e a d a s " 0 "

I 2 C d e v i c e s l a v e a d d r e s s

b 0

S A 5

S A 4

S A 6

S A 0

S A 3

S A 2

S A 1

Slave Address Register

- SIMAR

S I M C 0 R e g i s t e r

N o t i m p l e m e n t e d , r e a d a s " 0 "

I 2 C O n / O f f c o n t r o l

1 : e n a b l e

0 : d i s a b l e

N o t i m p l e m e n t e d

I 2 C M a s t e r / S l a v e a n d c l o c k c o n t r o l

S I M 2

S I M 1

S I M 0

b 0

S I M E N

N o t u s e d

I 2 C m o d e

N o t u s e d

b 7

S I M 1

S I M 0

S I M 2

2C Control Register

- SIMC0

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