HT83F60 datasheet(35/62 Pages) HOLTEK

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HT83FXX

Rev. 1.30

June 7, 2010

Interrupt Priority

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In case of simultaneous requests, the

accompanying table shows the priority that is applied.

Interrupt Source

Interrupt

Vector

HT83FXX

Priority

Time Base Interrupt

04H

Timer 0 Overflow

08H

Timer 1 Overflow

0CH

SIM Interrupt

14H

Suitable masking of the individual interrupts using the

INTC and INTCH registers can prevent simultaneous

occurrences.

Time Base Interrupt

Each device contains a Time Base whose correspond-

ing interrupt enable bits are known as ETBI and is lo-

cated in the INTC register. For a Time Base generated

interrupt to occur, the corresponding Time Base inter-

rupt enable bit must be first set. Time Base also has a

corresponding Time Base interrupt request flag, which

is known as TBF, also located in the INTC register.

When the master interrupt and corresponding timer in-

terrupt enable bits are enabled, the stack is not full, and

when the corresponding timer overflows a subroutine

call to the corresponding Time Base interrupt vector will

occur. The corresponding Program Memory vector loca-

tions for the Time Base is 04H. After entering the inter-

rupt execution routine, the corresponding interrupt

request flag, TBF will be reset and the EMI bit will be

cleared to disable other interrupts.

I N T C H R e g i s t e r

b 7

b 0

S I F

E S I I

N o i m p l e m e n t e d , r e a d a s " 0 "

C o n t r o l s e r i a l i n t e r f a c e i n t e r r u p t

1 : e n a b l e

0 : d i s a b l e

N o i m p l e m e n t e d , r e a d a s " 0 "

S e r i a l i n t e r f a c e i n t e r r u p t r e q u e s t f l a g

1 : a c t i v e

0 : i n a c t i v e

N o i m p l e m e n t e d , r e a d a s " 0 "

INTCH Register

A u t o m a t i c a l l y C l e a r e d b y I S R

M a n u a l l y S e t o r C l e a r e d b y S o f t w a r e

E E I

E M I

P r i o r i t y

I n t e r r u p t

P o l l i n g

H i g h

A u t o m a t i c a l l y D i s a b l e d b y I S R

C a n b e E n a b l e d M a n u a l l y

E T 0

L o w

E T 1

E S I I

T i m e r 0

I n t e r r u p t R e q u e s t F l a g T 0 F

T i m e r 1

I n t e r r u p t R e q u e s t F l a g T 1 F

S I M

I n t e r r u p t R e q u e s t F l a g S I F

T i m e B a s e

R e q u e s t F l a g E I F

Interrupt Structure

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