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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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dsPIC30F2012 Scheda tecnica(PDF) 75 Page - Microchip Technology |
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dsPIC30F2012 Scheda tecnica(HTML) 75 Page - Microchip Technology |
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75 / 206 page  © 2008 Microchip Technology Inc. DS70139F-page 75 dsPIC30F2011/2012/3012/3013 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal, up to the value specified in the Period register and is then reset to ‘0’. The TSYNC bit must be asserted to a logic ‘0’ (Asynchronous mode) for correct operation. Enabling LPOSCEN (OSCCON<1>) disables the normal Timer and Counter modes and enables a timer carry-out wake-up event. When the CPU enters Sleep mode, the RTC continues to operate, provided the 32 kHz external crystal oscillator is active and the control bits have not been changed. The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt is generated if enabled. The T1IF bit must be cleared in software. The respective Timer interrupt flag, T1IF, is located in the IFS0 register in the interrupt controller. Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T1IE. The timer interrupt enable bit is located in the IEC0 Control register in the interrupt controller. |
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