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UJA1075TW/5V0/WD Scheda tecnica(PDF) 4 Page - NXP Semiconductors |
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UJA1075TW/5V0/WD Scheda tecnica(HTML) 4 Page - NXP Semiconductors |
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4 / 53 page ![]() UJA1075_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 27 May 2010 4 of 53 NXP Semiconductors UJA1075 High-speed CAN/LIN core system basis chip 3. Ordering information [1] UJA1075TW/5V0xx versions contain a 5 V regulator (V1); UJA1075TW/3V3xx versions contain a 3.3 V regulator (V1); WD versions contain a watchdog. 4. Block diagram Table 1. Ordering information Type number[1] Package Name Description Version UJA1075TW/5V0/WD HTSSOP32 plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad SOT549-1 UJA1075TW/3V3/WD UJA1075TW/5V0 UJA1075TW/3V3 Fig 1. Block diagram SYSTEM CONTROLLER LIN BAT V1 UV UJA1075 SDI HS-CAN SCK SCSN SDO WAKE2 WAKE1 EN WDOFF LIN RXDL TXDL DLIN BAT BAT LIMP SPLIT RXDC TXDC CANL CANH V2 OSC TEMP INTN RSTN EXT. PNP CTRL VEXCC VEXCTRL V2 UV V2 V1 V1 V2 GND WAKE WBIAS 015aaa118 |
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