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UJA1075TW/5V0/WD Scheda tecnica(PDF) 5 Page - NXP Semiconductors

Il numero della parte UJA1075TW/5V0/WD
Spiegazioni elettronici  High-speed CAN/LIN core system basis chip
PDF  53 Pages
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Produttore elettronici  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo NXP - NXP Semiconductors

UJA1075TW/5V0/WD Scheda tecnica(HTML) 5 Page - NXP Semiconductors

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UJA1075_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 27 May 2010
5 of 53
NXP Semiconductors
UJA1075
High-speed CAN/LIN core system basis chip
5.
Pinning information
5.1 Pinning
5.2 Pin description
Fig 2.
Pin configuration
UJA1075
i.c.
BAT
i.c.
VEXCTRL
TXDL
TEST2
V1
VEXCC
RXDL
WBIAS
RSTN
i.c.
INTN
DLIN
EN
LIN
SDI
SPLIT
SDO
GND
SCK
CANL
SCSN
CANH
TXDC
V2
RXDC
WAKE2
TEST1
WAKE1
WDOFF
LIMP
015aaa119
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
17
20
19
22
21
24
23
26
25
32
31
30
29
28
27
Table 2.
Pin description
Symbol
Pin
Description
i.c.
1
internally connected; should be left floating
i.c.
2
internally connected; should be left floating
TXDL
3
LIN transmit data input
V1
4
voltage regulator output for the microcontroller (5 V or 3.3 V depending on
SBC version)
RXDL
5
LIN receive data output
RSTN
6
reset input/output to and from the microcontroller
INTN
7
interrupt output to the microcontroller
EN
8
enable output
SDI
9
SPI data input
SDO
10
SPI data output
SCK
11
SPI clock input
SCSN
12
SPI chip select input
TXDC
13
CAN transmit data input
RXDC
14
CAN receive data output
TEST1
15
test pin; pin should be connected to ground
WDOFF
16
WDOFF pin for deactivating the watchdog
LIMP
17
limp home output



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