DSP56L307 datasheet(5/104 Pages) FREESCALE

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DSP56L307 Technical Data, Rev. 6

Freescale Semiconductor

1-1

Signals/Connections

The DSP56L307 input and output signals are organized into functional groups as shown in Table 1-1. Figure 1-1

diagrams the DSP56L307 signals by functional group. The remainder of this chapter describes the signal pins in

each functional group.

Note:

This chapter refers to a number of configuration registers used to select individual multiplexed signal

functionality. Refer to the DSP56L307 User’s Manual for details on these configuration registers.

Table 1-1.

DSP56L307 Functional Signal Groupings

Functional Group

Number of

Signals

Power (VCC)

Ground (GND)

Clock

PLL

Address bus

Port A

Data bus

Bus control

Interrupt and mode control

Host interface (HI08)

Port B2

Enhanced synchronous serial interface (ESSI)

Ports C and D

Serial communication interface (SCI)

Port E4

Timer

OnCE/JTAG Port

Notes:

Port A signals define the external memory interface port, including the external address bus, data bus, and control signals.

The Clock Output (CLKOUT), BCLK, BCLK, CAS, and RAS[0–3] signals used by other DSP56300 family members are

supported by the DSP56L307 at operating frequencies up to 100 MHz. DRAM access is not supported above 100 MHz.

Port B signals are the HI08 port signals multiplexed with the GPIO signals.

Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.

Port E signals are the SCI port signals multiplexed with the GPIO signals.

There are 5 signal connections that are not used. These are designated as no connect (NC) in the package description (see

Chapter 3).

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