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STE100P Scheda tecnica(PDF) 23 Page - STMicroelectronics |
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STE100P Scheda tecnica(HTML) 23 Page - STMicroelectronics |
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23 / 31 page ![]() 23/31 STE100P Figure 10. MII Management Clock Timing Table 8. AC Specifications Symbol Parameter Test Condition Min. Typ. Max. Units MII Receive Timing Specification t1 RX-ER, RX-DV, RXD[3:0] Setup to RX-CLK 10 — ns t2 RX-ER, RX-DV, RXD[3:0] Hold After RX-CLK 10 — ns t3 RX-CLK High Pulse Width (100 Mbits/s) 14 26 ns RX-CLK High Pulse Width (10 Mbits/s) 200 ns t4 RX-CLK Low Pulse Width (100 Mbits/s) 14 26 ns RX-CLK Low Pulse Width (10 Mbits/s) 140 260 ns t5 RX-CLK Period (100 Mbits/s) 40 ns RX-CLK Period (10 Mbits/s) 400 ns MDC MDIO(O) MDIO(I) t1 t2 t3 t4 t5 t6 |
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