STE100P_06 datasheet(3/31 Pages) STMICROELECTRONICS

Il numero della parte	STE100P

Spiegazioni elettronici	10/100 FAST ETHERNET 3.3V TRANSCEIVER

PDF	31 Pages

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STE100P

PIN ASSIGNMENT DIAGRAM

Figure 4. Pin Connection

PIN DESCRIPTION

Table 2. Pin Description

Pin No.

Name

Type

Description

MII Data Interface

txd4

txd3

txd2

txd1

txd0

Transmit Data. The Media Access Controller (MAC) drives data to the STE100P

using these inputs.

txd4 is monitored only in Symbol (5B) Mode.

These signals must be synchronized to the tx_clk.

tx_en

Transmit Enable. The MAC asserts this signal when it drives valid data on the

txd inputs. This signal must be synchronized to the tx_clk.

tx_clk

I/O

Transmit Clock. Normally the STE100P drives tx_clk. Refer to the Clock

Requirements discussion in the Functional Description section.

25 MHz for 100 Mbps operation.

2.5 MHz for 10 Mbps operation.

28 29 30 31 32

59 58 57 56

53 52 51 50 49

fde

mf0

mf1

mf3

mf4

mf2

gnda

vcca

gnda

rdx3

mdc

mdio

vcce/i

ledr10

gnde/i

rx_dv

rxd0

rxd1

rdx2

vcce/i

D99TL457B

22 23 24 25 26

17 18 19 20 21

ledtr

ledl

leds

test_se

ledc

vcca

iref

gnda

vcca

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