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MB90F337 Scheda tecnica(PDF) 12 Page - fujitsu semiconductor |
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MB90F337 Scheda tecnica(HTML) 12 Page - fujitsu semiconductor |
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12 / 48 page ![]() MB90335 Series 12 DS07-13735-6E ■ BLOCK DIAGRAM F2MC-16LX CPU RAM ROM UART/SIO ch.0, ch.1 I2C SIO μDMAC P00 P07 P10 P17 P20 P27 P40 P47 P50 P54 P60 P67 X0, X1 RST MD0 to MD2 SIN0, SIN1 SOT0, SOT1 SCK0, SCK1 SCL0 SDA0 INT0 to INT7 DVP DVM HVP HVM HCON UTEST TOT0 TIN0 PPG0 to PPG3 PWC SIN SOT SCK * : Channel for use in 8-bit mode. 2 channels (ch.1, ch.3) are used in 16-bit mode. Note : I/O ports share pins with peripheral function (resources) . For details, refer to “ ■ PIN ASSIGNMENT” and “■ PIN DESCRIPTION”. Note also that pins used for peripheral function (resources) cannot serve as I/O ports. 16-bit reload timer External interrupt 16-bit PWC 8/16-bit PPG timer ch.0 to ch.3* Clock control circuit Interrupt controller I/O port (port 0, 1, 2, 4, 5, 6) USB (function) (HOST) |
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