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Electrical Specifications

Datasheet

NOTES:

VOS is measured overshoot voltage.

TOS is measured time duration above VID.

2.6.4

Die Voltage Validation

Overshoot events on processor must meet the specifications in Table 7 when measured

across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in

duration may be ignored. These measurements of processor die level overshoot must

be taken with a bandwidth limited oscilloscope set to a greater than or equal to

100 MHz bandwidth limit.

2.7

Signaling Specifications

Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling

technology. This technology provides improved noise margins and reduced ringing

through low voltage swings and controlled edge rates. Platforms implement a

termination voltage level for GTL+ signals defined as VTT. Because platforms implement

separate power planes for each processor (and chipset), separate VCC and VTT supplies

are necessary. This configuration allows for improved noise tolerance as processor

frequency increases. Speed enhancements to data and address busses have caused

signal integrity considerations and platform design methods to become even more

critical than with previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to

determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the

motherboard (see Table 14 for GTLREF specifications). Termination resistors (RTT) for

GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel

chipsets will also provide on-die termination; thus, eliminating the need to terminate

the bus on the motherboard for most GTL+ signals.

Figure 2.

VCC Overshoot Example Waveform

Example Overshoot Waveform

Time [us]

VID - 0.000

VID + 0.050

VOS

TOS

TOS: Overshoot time above VID

VOS: Overshoot above VID

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