MPC8377E datasheet(30/126 Pages) FREESCALE

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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

Figure 13 provides the AC test load for eTSEC.

Figure 13. eTSEC AC Test Load

Figure 14 shows the RMII receive AC timing diagram.

Figure 14. RMII Receive AC Timing Diagram

8.3

Management Interface Electrical Characteristics

The electrical characteristics specified here apply to MII management interface signals MDIO

(management data input/output) and MDC (management data clock).

Figure 15 provides the AC test load for eTSEC.

Figure 15. eTSEC AC Test Load

RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge

tRMRDV

4.0

—

RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge

tRMRDX

2.0

—

Note:

1 The symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII

receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference

(K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data

input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in

general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.

For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

Table 30. RMII Receive AC Timing Specifications (continued)

At recommended operating conditions with LVDD of 3.3 V ± 5%.

Parameter/Condition

Symbol1

Min

Typical

Max

Unit

Output

Z0 = 50 Ω

LVDD/2

RL = 50 Ω

REF_CLK

RXD[1:0]

tRMRDX

tRMR

tRMRH

tRMRR

tRMRF

CRS_DV

RX_ER

tRMRDV

Valid Data

Output

Z0 = 50 Ω

LVDD/2

RL = 50 Ω

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