MPC8377E datasheet(32/126 Pages) FREESCALE

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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

USB

Figure 16 shows the MII management AC timing diagram.

Figure 16. MII Management Interface Timing Diagram

9USB

This section provides the AC and DC electrical characteristics for the USB dual-role controllers.

MDC rise time (20%–80%)

tMDCR

—

MDC fall time (80%–20%)

tMDCF

—

Note:

1 The symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes

management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data

hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the

valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the

latter convention is used with the appropriate letter: R (rise) or F (fall).

2 This parameter is dependent on the system clock speed. (The maximum frequency is the maximum platform frequency

divided by 64.)

3 This parameter is dependent on the system clock speed. (That is, for a system clock of 267 MHz, the maximum frequency

is 8.3 MHz and the minimum frequency is 1.2 MHz; for a system clock of 375 MHz, the maximum frequency is 11.7 MHz and

the minimum frequency is 1.7 MHz.)

4 Guaranteed by design.

5 t

plb_clk is the platform (CSB) clock divided according to the SCCR[TSEC1CM].

Table 33. MII Management AC Timing Specifications (continued)

Parameter

Symbol1

Min

Typical

Max

Unit

Notes

MDC

tMDDXKH

tMDC

tMDCH

tMDCR

tMDCF

tMDDVKH

tMDKHDX

MDIO

(Input)

(Output)

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