M48Z2M1V datasheet(7/20 Pages) STMICROELECTRONICS

7 / 20 page

M48Z2M1Y, M48Z2M1V

Operation modes

Doc ID 5135 Rev 5

7/20

Operation modes

The M48Z2M1Y/V has its own power-fail detect circuit. The control circuitry constantly

monitors the single 5 V supply for an out of tolerance condition. When VCC is out of

tolerance, the circuit write protects the SRAM, providing a high degree of data security in the

midst of unpredictable system operations brought on by low VCC. As VCC falls below

approximately 3 V, the control circuitry connects the batteries which sustain data until valid

power returns.

Table 2.

Operating modes

Note:

X = VIH or VIL; VSO = battery backup switchover voltage.

2.1

READ mode

The M48Z2M1Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip

enable) is low. The device architecture allows ripple-through access of data from eight of

16,777,216 locations in the static storage array. Thus, the unique address specified by the

21 address inputs defines which one of the 2,097,152 bytes of data is to be accessed. Valid

data will be available at the data I/O pins within address access time (tAVQV) after the last

address input signal is stable, providing that the E (chip enable) and G (output enable)

access times are also satisfied. If the E and G access times are not met, valid data will be

available after the later of chip enable access time (tELQV) or output enable access time

(tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the

outputs are activated before tAVQV, the data lines will be driven to an indeterminate state

until tAVQV. If the address inputs are changed while E and G remain low, output data will

remain valid for output data hold time (tAXQX) but will go indeterminate until the next address

access.

Figure 4.

Address controlled, READ mode AC waveforms

Note:

Chip enable (E) and output enable (G) = low, WRITE enable (W) = high.

Mode

VCC

DQ0-

DQ7

Power

Deselect

3.0 to 3.6 V

4.5 to 5.5 V

VIH

High Z

Standby

WRITE

VIL

XVIL

DIN

Active

READ

VIL

VIH

DOUT

Active

READ

VIL

VIH

High Z

Active

Deselect

VSO to VPFD (min)

(1)

See Table 10 on page 15 for details.

High Z

CMOS standby

Deselect

≤ VSO(1)

High Z

Battery backup mode

AI02051

tAXQX

DATA VALID

A0-A20

DQ0-DQ7

tAVAV

tAVQV

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