M48Z2M1V datasheet(10/20 Pages) STMICROELECTRONICS

10 / 20 page

Operation modes

M48Z2M1Y, M48Z2M1V

10/20

Doc ID 5135 Rev 5

Table 4.

WRITE mode AC characteristics

2.3

Data retention mode

With valid VCC applied, the M48Z2M1Y/V operates as a conventional BYTEWIDE™ static

RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write

protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all

inputs are treated as “Don't care.”

If power fail detection occurs during a valid access, the memory cycle continues to

completion. If the memory cycle fails to terminate within the time tWP, write protection takes

place. When VCC drops below VSO, the control circuit switches power to the internal energy

source which preserves data.

The internal coin cells will maintain data in the M48Z2M1Y/V after the initial application of

VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system

power returns and VCC rises above VSO, the batteries are disconnected, and the power

supply is switched to external VCC. Write protection continues for tER after VCC reaches

VPFD to allow for processor stabilization. After tER, normal RAM operation can resume.

For more information on battery storage life refer to the application note AN1012.

Symbol

Parameter(1)

Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6V (except where

noted).

M48Z2M1Y

M48Z2M1V

Unit

–70

–85

Min

Max

Min

Max

tAVAV

WRITE cycle time

tAVEH

Address valid to chip enable high

tAVEL

Address valid to chip enable low

tAVWH

Address valid to WRITE enable high

tAVWL

Address valid to WRITE enable low

tDVEH

Input valid to chip enable high

tDVWH

Input valid to WRITE enable high

tEHAX

Chip enable high to address transition

tEHDX

Chip enable high to input transition

tELEH

Chip enable low to chip enable high

tWHAX

WRITE enable high to address transition

tWHDX

WRITE enable high to input transition

tWHQX

(2)(3)

CL = 5 pF (see Figure 9 on page 13).

If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

WRITE enable high to output transition

tWLQZ

(2)(3)

WRITE enable low to output Hi-Z

tWLWH

WRITE enable pulse width

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