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MPC5602DXLL Scheda tecnica(PDF) 9 Page - Freescale Semiconductor, Inc |
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MPC5602DXLL Scheda tecnica(HTML) 9 Page - Freescale Semiconductor, Inc |
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9 / 77 page ![]() Package pinouts and signal descriptions MPC5602D Microcontroller Data Sheet, Rev. 3.1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 9 Figure 3 shows the MPC5602D in the 64 LQFP package. Figure 3. 64 LQFP pin configuration (top view) 3.2 Pin muxing Table 3 defines the pin list and muxing for this device. Each entry of Table 3 shows all the possible configurations for each pin, via the alternate functions. The default function assigned to each pin after reset is indicated by AF0. Table 3. Functional port pin descriptions Port pin PCR register Alternate function1 Function Peripheral I/O direction2 Pad type RESET config. Pin No. 64 LQFP 100 LQFP Port A PA[0] PCR[0] AF0 AF1 AF2 AF3 — GPIO[0] E0UC[0] CLKOUT E0UC[13] WKUP[19]3 SIUL eMIOS_0 CGL eMIOS_0 WKPU I/O I/O O I/O I M Tristate 5 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PB[3] PC[9] PA[2] PA[1] PA[0] VPP_TEST VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[10] PB[0] PB[1] PC[6] PA[11] PA[10] PA[9] PA[8] PA[7] PA[3] PB[15] PB[14] PB[13] PB[12] PB[11] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC 64 LQFP |
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