CYWUSB6953_10 datasheet(26/68 Pages) CYPRESS

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CYRF69103

Document #: 001-07611 Rev *F

Page 26 of 68

Gain value for the register at location [0x38]:

3.3V = 0x40

3.0V = 0x40

2.85V = 0xFF

2.70V = 0xFF

Load register [0x38] with the gain values corresponding to the

appropriate voltage.

When using the 32 kHz oscillator the PITMRL/H must be read

until two consecutive readings match before sending/receiving

data. The following firmware example assumes the developer is

interested in the lower byte of the PIT.

Read_PIT_counter:

mov A, reg[PITMRL]

mov [57h], A

mov A, reg[PITMRL]

mov [58h],A

mov [59h], A

mov A, reg[PITMRL]

mov [60h], A

;;;Start comparison

mov A,[60h]

mov X, [59h]

sub A, [59h]

jz done

mov A, [59h]

mov X, [58h]

sub A, [58h]

jz done

mov X, [57h]

;;;correct data is in memory location 57h

done:

mov [57h], X

ret

15.2 Clock Architecture Description

The CYRF69103 clock selection circuitry allows the selection of

independent clocks for the CPU, Interval Timers, and Capture

Timers.

CPU Clock

The CPU clock, CPUCLK, can be sourced from the Internal

24 MHz oscillator. The selected clock source can optionally be

divided by 2n-1 where n is 0–7 (see Table 15-3 on page 27).

Table 15-1. Oscillator Trim Values vs. Voltage Settings

Supervisory ROM Table

Function

Table2 FCh

24 MHz IOSCTR at 3.30V

Table2 FDh

24 MHz IOSCTR at 3.00V

Table2 FEh

24 MHz IOSCTR at 2.85V

Table2 FFh

24 MHz IOSCTR at 2.70V

Table3 F8h

32 kHz LPOSCTR at 3.30V

Table3 F9h

32 kHz LPOSCTR at 3.00V

Table3 FAh

32 kHz LPOSCTR at 2.85V

Table3 FBh

32 kHz LPOSCTR at 2.70V

Table 15-2. CPU Clock Config (CPUCLKCR) [0x30] [R/W]

Bit #

Field

Reserved

Read/Write

–

Default

Bits 7:0

Reserved

Note The CPU speed selection is configured using the OSC_CR0 Register (Figure 15-2. on page 29).

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