CYWUSB6953_10 datasheet(29/68 Pages) CYPRESS

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CYRF69103

Document #: 001-07611 Rev *F

Page 29 of 68

Figure 15-2. Programmable Interval Timer Block Diagram

15.2.3 Internal Clock Trim

S yste m

Clo c k

C lo ck

Tim e r

C onfig uratio n

S tatus an d

Co n tro l

12 -b it

re lo a d

va lu e

12 -b it d o w n

co u n te r

12 -b it

re lo a d

cou n te r

In te rru p t

C o n tro lle r

Table 15-5. IOSC Trim (IOSCTR) [0x34] [R/W]

Bit #

Field

foffset[2:0]

Gain[4:0]

Read/Write

R/W

Default

The IOSC Calibrate register is used to calibrate the internal oscillator. The reset value is undefined but during boot the SROM

writes a calibration value that is determined during manufacturing test. The ‘D’ indicates that the default value is trimmed to

24 MHz at 3.30V at power on.

Bits 7:5

foffset [2:0]

This value is used to trim the frequency of the internal oscillator. These bits are not used in factory calibration and

are zero. Setting each of these bits causes the appropriate fine offset in oscillator frequency:

foffset bit 0 = 7.5 kHz

foffset bit 1 = 15 kHz

foffset bit 2 = 30 kHz

Bits 4:0

Gain [4:0]

The effective frequency change of the offset input is controlled through the gain input. A lower value of the gain

setting increases the gain of the offset input. This value sets the size of each offset step for the internal oscillator.

Nominal gain change (kHz/offsetStep) at each bit, typical conditions (24 MHz operation):

Gain bit 0 = –1.5 kHz

Gain bit 1 = –3.0 kHz

Gain bit 2 = –6 kHz

Gain bit 4 = –24 kHz

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