R5F363AMNFB datasheet(22/119 Pages) RENESAS

22 / 119 page

R01DS0033EJ0200 Rev.2.00

Page 22 of 115

Feb 07, 2011

M16C/63 Group

1. Overview

Note:

TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi (i = 0, 1, 5), SDAi, and SCLi can be

selected as CMOS output pins or N-channel open drain output pins.

Table 1.14

Pin Functions for the 80-Pin Package (2/2)

Signal Name

Pin Name

I/O

Power

Supply

Description

Serial interface

UART0 to UART2,

UART5

CTS0, CTS1,

CTS5

VCC1

Input pins to control data transmission

RTS0, RTS1,

RTS5

VCC1

Output pins to control data reception

CLK0, CLK1,

CLK5

I/O

VCC1

Transmit/receive clock I/O.

RXD0 to RXD2,

RXD5

VCC1

Serial data input.

TXD0 to TXD2,

TXD5

VCC1

Serial data output. (1)

CLKS1

VCC1

Output for the transmit/receive clock multiple-pin output

function.

UART0 to UART2,

UART5

I2C mode

SDA0 to SDA2,

SDA5

I/O

VCC1

Serial data I/O.

SCL0 to SCL2,

SCL5

I/O

VCC1

Transmit/receive clock I/O.

Serial interface

SI/O3, SI/O4

CLK3, CLK4

I/O

VCC1

Transmit/receive clock I/O.

SIN4

VCC1

Serial data input.

SOUT3, SOUT4

VCC1

Serial data output.

Multi-master I2C-bus

interface

SDAMM

I/O

VCC1

Serial data I/O (N-channel open drain output).

SCLMM

I/O

VCC1

Transmit/receive clock I/O (N-channel open drain output).

CEC I/O

CEC

I/O

VCC1

CEC I/O (N-channel open drain output).

Reference voltage

input

VREF

VCC1

Reference voltage input for the A/D and D/A converters.

A/D converter

AN0 to AN7

VCC1

Analog input.

AN0_0 to AN0_7

AN2_0 to AN2_7

VCC1

ADTRG

VCC1

External trigger input.

ANEX0, ANEX1

VCC1

Extended analog input.

D/A converter

DA0, DA1

VCC1

Output for the D/A converter.

I/O ports

P0_0 to P0_7

P2_0 to P2_7

P3_0 to P3_7

P5_0 to P5_7

P6_0 to P6_7

P8_0 to P8_7

P10_0 to P10_7

I/O

VCC1

8-bit CMOS I/O ports. A direction register determines

whether each pin is used as an input port or an output

port. A pull-up resistor may be enabled or disabled for

input ports in 4-bit units. P8_5 is an N-channel open drain

output port. No pull-up resistor is provided. P8_5 is an

input port for verifying the

NMI pin level and shares a pin

with

NMI.

P4_0 to P4_3

P7_0, P7_1

P7_6, P7_7

P9_0,

P9_2 to P9_7

I/O

VCC1

I/O ports having equivalent functions to P0. However,

P7_0 and P7_1 are N-channel open drain output ports.

No pull-up resistor is provided.

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