AD7280ABSTZ datasheet(31/48 Pages) AD

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AD7280A

Rev. 0 | Page 31 of 48

PD TIMER REGISTER

The PD timer register allows the user to configure a set time

after which the AD7280A is automatically powered down. The

AD7280A allows the user to set the PD timer to a value from

0 minutes to 36.9 minutes. The resolution of the PD timer is

71.5 sec. When using the PD timer in conjunction with the CBx

timers, the value programmed to the PD timer should exceed

that programmed to the CBx timer by at least 71.5 sec because

the PD timer takes priority over the CBx timers. The default

value of the PD timer register on power-up is 0x00.

Table 17. PD Timer Register Settings

Bits

Description

[D7:D3]

5-bit binary code to set the PD timer to a value

from 0 minutes to 36.9 minutes

[D2:D0]

Reserved; set to 000

READ REGISTER

The read register, in conjunction with Bits[D13:D12] and

Bit D0 of the control register, defines the read operations of the

AD7280A. To read back a single register from either a single

AD7280A or from a chain of AD7280A devices, the desired

read back a series of conversion results from either a single

AD7280A or from a chain of AD7280A devices, an address of

0x00 should be written to the read register. The default value of

the read register on power-up is 0x00.

Table 18. Read Register Settings

Bits

Description

[D7:D2]

6-bit binary address for the register to be read

[D1:D0]

Reserved; set to 00

CNVST CONTROL REGISTER

The CNVST control register allows the user to gate the input

signal from the CNVST pin.

Bit D0 of the CNVST control register allows the user to hold the

internal CNVST signal high regardless of any external noise or

glitches on the CNVST pin. This setting can be used in noisy

environments to prevent incorrect initiation of conversions.

When using the rising edge of CS to perform a software convert

start, it is recommended that the CNVST pin be gated out by

setting Bit D0 high (see the

section).

Conversion Start Format

Bit D1 of the CNVST control register allows the user to open a

window in the CNVST gate that allows a single CNVST pulse

through. The window is closed automatically following a falling

edge on the CNVST pin. To use this functionality, the user

should write 10 to Bits[D1:D0] of the CNVST control register

immediately before each conversion start request.

The default value of the CNVST control register on power-up

is 0x00.

Table 19. CNVST Control Register Settings

Bits

[D7:D2]

Bit

Description

000000

CNVST input not gated (default).

000000

CNVST input gated.

000000

Allow single CNVST pulse.

Additional CNVST pulses are gated.

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