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AS5245HQFT Scheda tecnica(PDF) 21 Page - ams AG |
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AS5245HQFT Scheda tecnica(HTML) 21 Page - ams AG |
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21 / 31 page ![]() www.austriamicrosystems.com/AS5245 Revision 1.5 21 - 31 AS5245 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n 9.3 3.3V / 5V Operation The AS5245 operates either at 3.3V ±10% or at 5V ±10%. This is made possible by an internal 3.3V Low-Dropout (LDO) Voltage regulator. The internal supply voltage is always taken from the output of the LDO, meaning that the internal blocks are always operating at 3.3V. For 3.3V operation, the LDO must be bypassed by connecting VDD3V3 with VDD5V (see Figure 15). For 5V operation, the 5V supply is connected to pin VDD5V, while VDD3V3 (LDO output) must be buffered by a 1...10µF capacitor, which is supposed to be placed close to the supply pin (see Figure 15). Note: The VDD3V3 output is intended for internal use only. It must not be loaded with an external load. The output voltage of the digital interface I/O’s corresponds to the voltage at pin VDD5V, as the I/O buffers are supplied from this pin. Figure 15. Connections for 5V / 3.3V Supply Voltages A buffer capacitor of 100nF is recommended in both cases close to pin VDD5V. Note that pin VDD3V3 must always be buffered by a capacitor. It must not be left floating, as this may cause an instable internal 3.3V supply voltage, which may lead to larger than normal jitter of the measured angle. Internal VDD LDO I N T E R F A C E VSS VDD5V VDD3V3 100n 4.5 - 5.5V + 1... 10µF DO PWM CLK CSn PDIO Internal VDD LDO I N T E R F A C E VSS VDD5V VDD3V3 3.0 - 3.6V + DO PWM CLK CSn PDIO 100n 5V Operation 3.3V Operation |
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